Hydrodata.Info: A Web Service For Hydrological Time Series Visualization

Fast, attractive and efficient visualization in the form of time series charts is important for communicating the results of hydrologic research to the public. While there are many popular tools and application programming interfaces (API\u27s) for creating time-series charts on the web (Google charts, HighCharts and others), none of these tools are specially tailored for hydrologic time-series observations and forecasts. This presentation introduces the concept of a free web service for generating hydrologic time-series charts from any combination of data sources available in the Consortium of Universities for Advancement of Hydrologic Science (CUAHSI)\u27s Hydrologic information System. This catalog of distributed services provides a growing volume of hydrological and meteorological data from many parts of the world using a standard WaterML format. By using a Representational State Transfer (REST) API, the end user can specify the time period, data source, site and variable to be displayed in the chart. Several pre-defined charts frequently used in hydrology (logarithmic plot, rainfall accumulation plot, multiple season plot, combined rainfall-runoff plot) are supported by the API. Special care has been taken for handling periods of missing data, displaying sporadic observations, and combining multiple time series in the chart. The size, quality and format of the chart can also be specified by the user. Once a chart image is generated, it can be cached on the hydrodata.info server for improving the speed of repeated requests. The hydrological time series chart API is already used in the hydrodata.cz and grafy.plaveniny.cz web portals for providing user-friendly access to hydrologic information from the Czech Republic and neighbouring countries

Increasing the level of abstraction in FPGA-based designs

Traditional design techniques for FPGAs are based on using hardware description languages, with functional and post-place-and-route simulation as a means to check design cor-rectness and remove detected errors. With large complexity of things to be designed it is necessary to introduce new de-sign approaches that will increase the level of abstraction while maintaining the necessary efficiency of a computation performed in hardware that we are used to today. This paper presents one such methodology that builds upon existing re-search in multithreading, object composability and encapsu-lation, partial runtime reconfiguration, and self adaptation. The methodology is based on currently available FPGA de-sign tools. The efficiency of the methodology is evaluated on basic vector and matrix operations. 1

X-ray microscopy of living multicellular organisms with the Prague Asterix Iodine Laser System

Soft X-ray contact microscopy (SXCM) experiments have been performed using the Prague Asterix Iodine Laser System (PALS). Laser wavelength and pulse duration were λ = 1.314 μm and τ (FWHM) = 450 ps, respectively. Pulsed X rays were generated using teflon, gold, and molybdenum targets with laser intensities I ≥ 1014 W/cm2. Experiments have been performed on the nematodes Caenorhabditis elegans. Images were recorded on PMMA photo resists and analyzed using an atomic force microscope operating in contact mode. Our preliminary results indicate the suitability of the SXCM for multicellular specimens

Shock pressure induced by 0.44 [mu]m laser radiation on aluminum targets

Shock pressure generated in aluminum targets due to the interaction of 0.44 μm (3 ω of iodine laser) laser radiation has been studied. The laser intensity profile was smoothed using phase zone plates. Aluminum step targets were irradiated at an intensity I ≈ 1014 W/cm2. Shock velocity in the aluminum target was estimated by detecting the shock luminosity from the target rear using a streak camera to infer the shock pressure. Experimental results show a good agreement with the theoretical model based on the delocalized laser absorption approximation. In the present report, we explicitly discuss the importance of target thickness on the shock pressure scaling

Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA

A high performance RLS lattice filter with the estimation of an unknown order and forgetting factor of identified system was developed and implemented as a PCORE coprocessor for Xilinx EDK. The coprocessor implemented in FPGA hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programming and debugging of hardware accelerated DSP applications. The RLS lattice core extended by the order and forgetting factor estimation was implemented using the logarithmic numbers system (LNS) arithmetic. An optimal mapping of the RLS lattice onto the LNS arithmetic units found by the cyclic scheduling was used. The schedule allows us to run four independent filters in parallel on one arithmetic macro set. The coprocessor containing the RLS lattice core is highly configurable. It allows to exploit the modular structure of the RLS lattice filter and construct the pipelined serial connection of filters for even higher performance. It also allows to run independent parallel filters on the same input with different forgetting factors in order to estimate which order and exponential forgetting factor better describe the observed data. The FPGA coprocessor implementation presented in the paper is able to evaluate the RLS lattice filter of order 504 at 12 kHz input data sampling rate. For the filter of order up to 20, the probability of order and forgetting factor hypotheses can be continually estimated. It has been demonstrated that the implemented coprocessor accelerates the Microblaze solution up to 20 times. It has also been shown that the coprocessor performs up to 2.5 times faster than highly optimized solution using 50 MIPS SHARC DSP processor, while the Microblaze is capable of performing another tasks concurrently

Research Article Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA

A high performance RLS lattice filter with the estimation of an unknown order and forgetting factor of identified system was developed and implemented as a PCORE coprocessor for Xilinx EDK. The coprocessor implemented in FPGA hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programming and debugging of hardware accelerated DSP applications. The RLS lattice core extended by the order and forgetting factor estimation was implemented using the logarithmic numbers system (LNS) arithmetic. An optimal mapping of the RLS lattice onto the LNS arithmetic units found by the cyclic scheduling was used. The schedule allows us to run four independent filters in parallel on one arithmetic macro set. The coprocessor containing the RLS lattice core is highly configurable. It allows to exploit the modular structure of the RLS lattice filter and construct the pipelined serial connection of filters for even higher performance. It also allows to run independent parallel filters on the same input with different forgetting factors in order to estimate which order and exponential forgetting factor better describe the observed data. The FPGA coprocessor implementation presented in the paper is able to evaluate the RLS lattice filter of order 504 at 12 kHz input data sampling rate. For the filter of order up to 20, the probability of order and forgetting factor hypotheses can be continually estimated. It has been demonstrated that the implemented coprocessor accelerates the Microblaze solution up to 20 times. It has also been shown that the coprocessor performs up to 2.5 times faster than highly optimized solution using 50 MIPS SHARC DSP processor, while the Microblaze is capable of performing another tasks concurrently

Pipelined Implementations Of The A Priori Error-Feedback Lsl Algorithm Using Logarithmic Arithmetic

In this paper we present several implementations of the Modified A Priori Error-Feedback LSL (EF-LSL) algorithm [1] on the VIRTEX FPGA. Its computational parallelism and pipelinabilty are important advantages. Internally, the computations are based on the logarithmic number system. We compare 32-bit (SINGLE-ALU or DUAL-ALU version) and 20-bit (QUADRI-ALU versions). We show that the LNS implementation can outperform the standard DSP solutions based on 32-bit floating-point processors